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Start the LogicPython Modbus RTU slave worker using a pre-opened UART channel.
from cubloc import SetModbus SetModbus(channel: int, slaveAddress: int, coils: object, discreteInputs: object, inputRegisters: object, holdingRegisters: object, memoryLock: object, returnInterval: int = 0)
channel number. OpenCom must already be called for this channel.coils per byte).slaveAddress is outside the supported range.import struct import _thread from cubloc import OpenCom, SetModbus, High, Low, In, Input, Output, AdIn, Delay # Coils 0-3 -> digital outputs on GP14, GP16, GP18, GP20 # Discrete inputs 0-2 <- digital inputs on GP6, GP8, GP10 # Input registers 0-2 <- ADC readings on ADC0 (GP26), ADC1 (GP27), ADC2 (GP28) # Holding register 0 -> setpoint value written by the Modbus master OUTPUT_PINS = (14, 16, 18, 20) INPUT_PINS = (6, 8, 10) ADC_CHANS = (0, 1, 2) # Allocate Modbus memory regions coils = bytearray(1) # 8 coils (1 byte, bits 0-3 used) discrete_inputs = bytearray(1) # 8 discrete inputs (1 byte, bits 0-2 used) input_regs = bytearray(6) # 3 input registers x 2 bytes each holding_regs = bytearray(2) # 1 holding register x 2 bytes mem_lock = _thread.allocate_lock() # Configure physical I/O for pin in OUTPUT_PINS: Output(pin) Low(pin) for pin in INPUT_PINS: Input(pin) # Open UART1 (GP4 = TX, GP5 = RX) at 9600 baud, 8N1 OpenCom(1, 9600, 0) # Start Modbus RTU slave, address 1 SetModbus(1, 1, coils, discrete_inputs, input_regs, holding_regs, mem_lock) # Main loop: mirror Modbus memory to/from physical I/O every 10 ms while True: with mem_lock: # Drive output pins from coil bits (master writes coils 0-3) for i, pin in enumerate(OUTPUT_PINS): if coils[0] & (1 << i): High(pin) else: Low(pin) # Capture digital inputs and store as discrete-input bits (master reads) din_byte = 0 for i, pin in enumerate(INPUT_PINS): if In(pin): din_byte |= (1 << i) discrete_inputs[0] = din_byte # Capture ADC readings and store in input registers (big-endian, master reads) for i, ch in enumerate(ADC_CHANS): struct.pack_into('>H', input_regs, i * 2, AdIn(ch)) # Read setpoint value from holding register 0 (master writes) setpoint = struct.unpack_from('>H', holding_regs, 0)[0] Delay(10)